1. Field of the Invention
The present invention relates to a booster circuit and a semiconductor integrated circuit having the booster circuit, and more particularly, to a booster circuit for boosting a supply voltage using MOS capacitors.
2. Description of the Related Art
Recently, semiconductor integrated circuits have been designed to realize fine circuitry and large-scale integration and to operate at a lower supply voltage (driving voltage) for the purpose of reducing power consumption. Therefore, a booster circuit for boosting and supplying a supply voltage has been employed, in order to supply an optimum voltage to each circuit.
Namely, in the prior art, when voltages other than external supply voltages VCC and VSS must be used within a chip having a semiconductor integrated circuit formed thereon, voltages of levels desired within the chip are generated by the semiconductor integrated circuit itself for due use. This kind of power supply is usually referred to as an internal power supply.
Specifically, when a dynamic random access memory (DRAM) is taken for instance, a cell transistor serving as a memory cell is generally formed with an N-channel type transistor. In order to operate the cell transistor so that the threshold voltage Vth thereof remains unknown, a voltage having a level equal to or higher than a level VCC+Vth must be applied to the gate of the cell transistor. A voltage level higher than the supply voltage VCC is referred to as a booster level. A circuit for generating a voltage of a booster level, that is, a booster voltage is referred to as a booster circuit.
The booster circuit is designed to, for example, carry out a boost operation using MOS capacitors. Along with the trend toward a lower supply voltage, there arises a problem that the margin of a low-voltage operating point decreases. Under the circumstances, a demand exists for a booster circuit whose low-voltage operating point margin can be expanded while an increase in the area occupied by the circuit is suppressed.
The prior art booster circuit and problems associated with the prior art booster circuit will be described in detail later with reference to drawings.